Design-Reuse

Modelsim and gate verilog IP Listing

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ... The ...
Electronic Design

Simulation Demonstrates PCIe Core IP's Capabilities

Intellectual property (IP) provider CAST Inc. has created a free, downloadable simulation model of its PCI Express (PCIe) IP core. The PCIe Core Backend Model (CBM) Demo of the CAST CPXP-EP PCI ...
Design-Reuse

Xilinx Verilog modelsim IP Listing

The USB20SR is a USB 2.0 Device, Software based enumeration RAM Interface IP Core. The core is RAM based with 32-bit Avalon interface and supports ULPI interface and Software Enumeration. It ... The ...