Tech Xplore on MSN

AI learns to perform analog layout design

Researchers at Pohang University of Science and Technology (POSTECH) have developed an artificial intelligence approach that ...
EDN

Timing Closure Using Layout Based Design Process

Chung-Kuan Cheng received a Ph.D. degree inelectrical engineering and computer sciences from University ofCalifornia, Berkeley in 1984. From 1984 to 1986 he was a senior CADengineer at Advanced Micro ...
Semiconductor Engineering

The Process Design Kit: Protecting Design Know-How

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each ...
EDN

Analog IC co-design for latch-up compliance

Design of power/driver ICs in compliance with latchup qualification requirements involves a conceptually different approach in comparison with digital LV (low voltage) ICs. The LV ICs’ electrostatic ...
Design-Reuse

Optimizing Analog Layouts: Techniques for Effective Layout Matching

In analog layout design, precise layout matching techniques are crucial to ensure the accuracy and performance of the circuit so that transistors exhibit similar electrical properties (i.e.
Semiconductor Engineering

Tuning Design And Process For High-NA EUV Stitching

Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, ...
Design-Reuse

A point of view on ''Analog Design and Layout Migration automation in the AI era''

The design teams typically invest years and numerous iterations to validate IP and produce a functioning chip. Once this validation is complete, they create derivatives of the silicon-proven IP, often ...